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SIP41108
New Product
Vishay Siliconix
Half-Bridge N-Channel Programmable 1-A MOSFET Driver for DC/DC Conversion with Adjustable High Side Propagation Delay
FEATURES
D D D D D D D D D 8-V or 12-V Low-Side Gate Drive Undervoltage Lockout Internal Bootstrap Diode Adaptive Shoot-Through Protection Synchronous MOSFET Disable Shutdown Control Adjustable High-Side Propagation Delay Switching Frequency Up to 1 MHz Drive MOSFETs In 5- to 48-V Systems
APPLICATIONS
D D D D D D Multi-Phase DC/DC Conversion High Current Synchronous Buck Converters High Frequency Synchronous Buck Converters Asynchronous-to-Synchronous Adaptations Mobile Computer DC/DC Converters Desktop Computer DC/DC Converters
DESCRIPTION
SIP41108 is a high-speed half-bridge MOSFET driver with adaptive shoot-through protection for use in high frequency, high current, multiphase dc-to-dc synchronous rectifier buck power supplies. It is designed to operate at switching frequencies up to 1 MHz. The high-side driver is bootstrapped to allow driving n-channel MOSFETs. SIP41108 comes with adaptive shoot-through protection to prevent simultaneous conduction of the external MOSFETs. The high-side turn on delay is programmable via an external capacitor. The 8-V regulator sets the high-side gate drive. The low-side driver supply, PVDD, must be externally connected to either VDRV or VDD for 8-V or 12-V gate drive respectively. The SIP41108 is assembled in a lead (Pb)-free PowerPAKr TSSOP-16 package and is specified to operate over the industrial operating range of -40C to 85C.
FUNCTIONAL BLOCK DIAGRAM
+5 to 48 V +12 V
VDRV
PVDD
VDD
BOOT
OUTH
SIP41108
PWM Controller SD ENSYNC LX VOUT
DELAY
OUTL
GND
GND
GND
8-V High-Side and 12-V Low-Side Gate Drive Configuration
Document Number: 73373 S-51104--Rev. B, 13-Jun-05 www.vishay.com
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SIP41108
Vishay Siliconix
New Product
ABSOLUTE MAXIMUM RATINGS (ALL VOLTAGES REFERENCED TO GND = 0 V)
VDD, PWM, ENSYNC, DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 15 V LX, BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 55 V BOOT to LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to 15 V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 150_C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125_C Power Dissipationa,b TSSOP-16 PowerPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 W Thermal Impedance (QJA)a,b TSSOP-16 PowerPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38_C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 26.3 mW/_C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE (ALL VOLTAGES REFERENCED TO GND = 0 V)
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8 V to 13.2 V VLX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 V CBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 nF to 1 mF VBOOT-LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85_C
SPECIFICATIONSa
Test Conditions Unless Specified p Parameter Power Supplies
Supply Voltage Quiescent Current Supply Current Shutdown Current VDD IDDQ IDD ISD PWM Non-Switching fPWM = 100 kHz CLOAD = 3 nF kHz, SD = 0 V, TA = 25_C SD = 0 V PVDD = VDD PVDD = VDRV 10.8 5.0 11.5 10.0 0.1 0.8 1 5 mA 13.2 8.5 mA V
Limits Mina Typb Maxa Unit
Symbol
VDD = 12 V, VBOOT - VLX = 8 V, TA = -40 to 85_C
Reference Voltage
Break-Before-Make VBBM 2.5 V
PWM Input
Input High Input Low Bias Current VIH VIL IB VIH VIL IB IB SD = VDD 4.0 "0.3 4.0 VDD 1.0 "1 V mA
ENSYNC, SD Inputs
Input High Input Low Bias Current (ENSYNC) Bias Current (SD) VDD 1.0 "1 15 V mA
Bootstrap Diode
Forward Voltage VF IF = 40 mA, TA = 25_C 0.7 0.85 1.0 V
MOSFET Drivers
High-Side Drive Current IPKH(source) IPKH(sink) IPKL(source) Low-Side Drive Current IPKL(sink) IPKL(source) IPKL(sink) www.vishay.com VBOOT - VLX = 8 V VDRV = 8 V VDRV = 12 V PVDD = VDRV PVDD = VDD 0.8 1.0 0.9 1.2 1.4 1.8 Document Number: 73373 S-51104--Rev. B, 13-Jun-05 A
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SIP41108
New Product
SPECIFICATIONSa
Test Conditions Unless Specified Parameter MOSFET Drivers
High-Side High Side Driver Impedance RDH(source) RDH(sink) RDL(source) Low-Side Low Side Driver Impedance RDL(sink) RDL(source) RDL(sink) High-Side Rise Time High-Side Fall Time High-Side Rise Time Bypass High-Side Fall Time Bypass High-Side High Side Propagation Delay td(off)H td(on)H trL L trH tfH VBOOT - VLX = 8 V LX = GND V, VDRV = 8 V VDRV = 12 V PVDD = VDRV PVDD = VDD 2.3 1.9 2.9 1.3 2.4 1.2 45 35 45 35 20 30 PVDD = VDRV PVDD = VDD PVDD = VDRV PVDD = VDD 65 65 30 30 15 20 ns 4.2 3.5 5.2 2.4 4.3 2.2 W
Vishay Siliconix
Limits Mina Typb Maxa Unit
Symbol
VDD = 12 V, VBOOT - VLX = 8 V, TA = -40 to 85_C
10% - 90% VBOOT - VLX = 8 V CLOAD = 3 nF 90%, 10% - 90% VBOOT - VLX = 12 V CLOAD = 3 nF 90%, See Timing Waveforms 10% - 90%, VBOOT - VLX = 8 V CLOAD = 3 nF 10% - 90%, VBOOT - VLX = 12 V CLOAD = 3 nF 10% - 90%, VBOOT - VLX = 8 V CLOAD = 3 nF 10% - 90%, VBOOT - VLX = 12 V CLOAD = 3 nF See Timing Waveforms
Low-Side Low Side Rise Time
Low-Side Low Side Fall Time
tfL td(off)L td(on)L
Low-Side Low Side Propagation Delay
LX Timer
PHASE Falling Time-out tLX 380 ns
VDRVRegulator
Output Voltage Output Current Current Limit Line Regulation Load Regulation VDRV IDRV ILIM LNR LDR VDRV = 0 V VCC = 10.8 V to 13.2 V 5 mA to 80 mA 120 7.6 8 80 200 0.05 0.1 8.4 100 280 0.5 1.0 V mA %/V %
VDRV Regulator UVLO
VDRV Rising VDRV Falling Hysteresis VUVLO2
Hyst
VDRV= VDD VDRV = VDD 100
6.7 6.4 300
7.2 6.9 500
V mV
High-Side Undervoltage Lockout
Threshold VUVHS LX Falling 2.5 3.35 4.0 V
VDD Undervoltage Lockout
Threshold Power on Reset Time VUVLO1 POR 5.0 5.3 2.5 5.6 V ms
Thermal Shutdown
Temperature Hysteresis TSD TH Temperature Rising Temperature Falling 165 25 _C
Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (-40_ to 85_C). b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing and are measured at VDD = 12 V unless otherwise noted.
Document Number: 73373 S-51104--Rev. B, 13-Jun-05
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SIP41108
Vishay Siliconix
TIMING WAVEFORMS
PWM 50% 90% 10% tfH 90% OUTL td(off)H 10% 90% 10% td(on)H 10% trH 50% 90%
New Product
OUTH
trL td(off)L
tfL
LX 2.5 V
td(on)L
PIN CONFIGURATION AND TRUTH TABLE
TSSOP-16 PowerPAK
NC OUTH BOOT SD PWM DELAY AGND PGND 1 2 3 4 5 6 7 8 Top View 16 15 14 13 12 11 10 9 NC LX ENSYNC VDRV PVDD VDD OUTL NC
TRUTH TABLE
PWM
L H L H X
SD
H H H H L
ENSYNC
L L H H X
OUTH
L H L H L
OUTL
L L H L L
ORDERING INFORMATION
Part Number
SIP41108DQP-T1-E3
Eval Kit Marking
41108 SIP41108DB
Temperature Range
-40 to 85_C
Temperature Range
-40 to 85_C
PIN DESCRIPTION
Pin Number
1, 9, 16 2 3 4 5 6 7 8 10 11 12 13 14 15 www.vishay.com
Name
NC OUTH BOOT SD PWM DELAY AGND PGND OUTL VDD PVDD VDRV ENSYNC LX No Connection 8-V High-side MOSFET gate drive
Function
Bootstrap supply for high-side driver. A capacitor connects between BOOT and LX. Shuts down the driver IC Input signal for the MOSFET drivers Connection for the highside delay adjustment capacitor. Analog ground. Exposed pad is connected to AGND. Power ground Synchronous or low-side MOSFET gate drive 12-V supply. Connect a bypass capacitor w1 mF from here to ground. Low side driver supply. Connect to VDRV for 8-V Gate Drive or to VDD for 12-V drive. 8-V Voltage Regulator Output. Connect a bypass capacitor w1 mF from here to ground Enables OUTL, the driver for the synchronous MOSFET Connection to source of high-side MOSFET, drain of the low-side MOSFET, and the inductor Document Number: 73373 S-51104--Rev. B, 13-Jun-05
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SIP41108
New Product
FUNCTIONAL BLOCK DIAGRAM
VDRV VDD +8-V Regulator BOOT
Vishay Siliconix
SD
UVLO OTP UVLO
OUTH
LX Delay DELAY PWM ENSYNC - + VBBM (2.5 V)
PVDD OUTL
GND
PGND
PVDD
Figure 1.
DETAILED OPERATION
PWM The PWM pin controls the switching of the external MOSFETs. The driver logic operates in a noninverting configuration. The PWM input stage should be driven by a signal with fast transition times, like those provided by a PWM controller or logic gate, (<200 ns). The PWM input functions as a logic input and is not intended for applications where a slow changing input voltage is used to generate a switching output when the input switching threshold voltage is reached. The PWM amplitude is 5 V but can go up to VDD. Low-Side Driver The supplies for the low-side driver are VDD and GND. During shutdown, OUTL is held low. High-Side Driver The high-side driver is isolated from the substrate to create a floating high-side driver so that an n-channel MOSFET can be used for the high-side switch. The supplies for the high-side driver are BOOT and LX. The voltage is supplied by a floating bootstrap capacitor, which is continually recharged by the switching action of the output. During shutdown OUTH is held low. Gate Drive Voltage (VDRV) Regulator An integrated 80-mA, 8-V regulator supplies voltage to the VDRV pin and it current limits at 200-mA typical when the output of the regulator is shorted to ground. A capacitor (1 mF minimum) must be connected to the VDRV pin to stabilize the regulator output, and the voltage on VDRV is supplied to the integrated bootstrap diode. VDRV is used to recharge the bootstrap capacitor and can be used to power the low-side driver. The VDRV can be externally connected to VDD to bypass the 8-V regulator and allow 12-V high-side gate drive. If VDRV is connected to VDD the system voltage should not exceed 43 V.
Document Number: 73373 S-51104--Rev. B, 13-Jun-05
www.vishay.com
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SIP41108
Vishay Siliconix
New Product
Bootstrap Circuit The internal bootstrap diode and a bootstrap capacitor form a charge pump that supplies voltage to the BOOT pin. An integrated bootstrap diode replaces the external Schottky diode needed for the bootstrap circuit; only a capacitor is necessary to complete the bootstrap circuit. The bootstrap capacitor is sized according to,
CBOOT = (QGATE/DVBOOT-LX) x 10
MOSFET. Choose a MOSFET with lower gate resistance to reduce this effect. If necessary, choose a capacitor value that prevents MOSFET conduction under worst-case temperature and manufacturing conditions. Propagation delay is increased according to the ratio of 1 ns/pF. Synchronous MOSFET Enable Under light load conditions, efficiency can be increased by disabling the synchronous MOSFET, thus avoiding the gate charge losses of the synchronous MOSFET. When ENSYNC is low, OUTL is forced low. When high, the low-side driver operates normally. ENSYNC should be driven by a 5-V signal but can go up to VDD Shutdown The driver enters shutdown mode when SD goes low. Both OUTL and OUTH go low during shutdown. Shutdown current is less than 1 mA. VDD Bypass Capacitor MOSFET drivers draw large peak currents from the supplies when they switch. A local bypass capacitor is required to supply this current and reduce power supply noise. Connect a 1-mF ceramic capacitor as close as practical between the VDD and GND pins. Undervoltage Lockout Undervoltage lockout prevents control of the circuit until the supply voltages reach valid operating levels. The UVLO circuit forces OUTL and OUTH to low when VDD is below its specified voltage. A separate UVLO forces OUTH low when the voltage between BOOT and LX is below the specified voltage. Thermal Protection If the die temperature rises above 165_C, the thermal protection disables the drivers. The drivers are re-enabled after the die temperature has decreased below 140_C.
where QGATE is the gate charge needed to turn on the high-side MOSFET and DVBOOT-LX is the amount of droop allowed in the bootstrapped supply voltage when the high-side MOSFET is driven high. The bootstrap capacitor value is typically 0.1 mF to 1 mF. The bootstrap capacitor voltage rating must be greater than VDD + 12 V to withstand transient spikes and ringing. Shoot-Through Protection The external MOSFETs are prevented from conducting at the same time during transitions. Break-before-make circuits monitor the voltages on the LX pin and the OUTL pin and control the switching as follows: When the signal on PWM goes low, OUTH will go low after an internal propagation delay. After the voltage on LX falls below 2.5 V by the inductor action, the low-side driver is enabled and OUTL goes high after some delay. When the signal on PWM goes high, OUTL will go low after an internal propagation delay. After the voltage on OUTL drops below 2.5 V, the high-side driver is enabled and OUTH will go high after an internal propagation delay. If LX does not drop below 2.5 V within 380 ns after OUTH goes low, OUTL is forced high until the next PWM transition. Delay The addition of a capacitor between DELAY and GND will increase the propagation delay time for OUTH going high. Delay capacitance may be added to prevent shoot through current in the low-side MOSFET due to the finite time between OUTL going low and the continuing conduction of the low-side
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Document Number: 73373 S-51104--Rev. B, 13-Jun-05
SIP41108
New Product
TYPICAL CHARACTERISTICS
105 95 85 75 IDD (mA) IDD (mA) 65 55 45 35 25 15 5 0 1 2 3 CLOAD (nF) 4 5 200 kHz 1 MHz 500 kHz
Vishay Siliconix
IDD vs. CLOAD vs. Frequency (PVDD = VDD)
VDD = 12 V
90 80 70 60 50 40 30 20 10 0 0
IDD vs. CLOAD vs. Frequency (PVDD = VDRV)
VDD = 12 V
1 MHz
500 kHz
200 kHz
1
2 3 CLOAD (nF)
4
5
140.0 120.0 100.0 td(on)H (ns) 80.0 60.0 40.0 20.0 0.0 0 10
High-Side Turn On Delay vs.CDELAY
20
30
40
50 60 70 CDELAY (pF)
80
90 100 110
TYPICAL WAVEFORMS
Figure 2. PWM Signal vs. HS Gate, LS Gate and LX (Rising)
PWM IN 5 V/div OUTH Gate 20 V/div
Figure 3. PWM Signal vs. HS Gate, LS Gate and LX (Falling)
PWM IN 5 V/div OUTH Gate 20 V/div
OUTL Gate 10 V/div
OUTL Gate 10 V/div
VLX 10 V/div
VLX 10 V/div 40 ns/div
40 ns/div
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?73373. Document Number: 73373 S-51104--Rev. B, 13-Jun-05 www.vishay.com
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Legal Disclaimer Notice
Vishay
Notice
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale.
Document Number: 91000 Revision: 08-Apr-05
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